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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com cs5461 single phase bi-directional power/energy ic features z energy data linearity: 0.1% of reading over 1000:1 dynamic range z on-chip functions: energy, i ? v, i rms and v rms , energy-to-pu lse conversion z ac/dc system calibrations z meets accuracy spec for iec 687/1036, jis z power consumption <12 mw z on-chip temperature sensor z voltage sag detect z adjustable input r ange on cu rrent channel z phase compensation z gnd-referenced signal s with single supply z on-chip 2.5 v reference (25 ppm/c typ) z simple three-wire digi tal serial interface z power supply monitor z interface optimized for shunt sensor z mechanical counter/s tepper motor drive z smart ?auto-boot? mode from serial eeprom with no mi crocontroller. z power supply configurations va+ = +5 v; va- = 0 v; vd+ = +3.3 v to +5 v description the cs5461 is an integrated power measure- ment device which combines two ? adcs, high speed power calculation functions, and a serial interface on a single chip . it is designed to accu- rately measure instantaneous current and voltage, and calculate: instantaneous power, average power, i rms , and v rms , for sin- gle-phase 2- or 3-wire power metering applications. the cs5461 can interface to a low-cost shunt resistor or transformer for current measurement, and to a resistive divider or poten- tial transformer for voltage measurement. the cs5461 features a bi-directional serial interface for communication with a micro-controller and a programmable energy-to-pulse output function. cs5461 has on-chip functionality to facilitate ac or dc system-level calibr ation. additional fea- tures include on-chip temperature sensor, voltage sag detection, and phase compensation. ordering in formation: CS5461-IS -40 c to +85 c 24-pin ssop pga va+ vd+ iin+ iin- vin+ vin- vrefin vrefout va- xin xout cpuclk dgnd cs sdo sdi sclk int fout high pass filter voltage reference system clock /k clock generator serial interface e-to-f power monitor pfmon x1 reset digital filter calibration edir high pass filter mode eout x10 power calculation engine 4th order ? modulator 2nd order ? modulator temperature sensor digital filter x10,x50 jan 04 ds546pp2
cs5461 2 ds546pp2 table of contents 1. general description ....................................................................................................... 5 2. pin description ........................................................................................................... ........ 6 3. characteristics/specifications ................................................................................. 8 analog characteristics ................................................................................................ 8 voltage reference........................................................................................................ 10 5 v digital characteristics......................................................................................... 11 3 v digital characteristics......................................................................................... 11 switching characteristics ........................................................................................ 12 3.1 theory of operation ....................................................................................................... .. 14 3.1.1 high-rate digital low-pa ss filters ..................................................................... 14 3.1.2 digital compensation filters ............................................................................... 14 3.1.3 digital high-pass filters ...................................................................................... 14 3.1.4 gain and dc offset adjustment .......................................................................... 14 3.1.5 average (real) power computation ................................................................... 14 3.1.6 rms computations ............................................................................................. 15 3.2 performing measurements ............................................................................................... 15 3.3 cs5461 linearity performance ........................................................................................ 15 4. functional description ............................................................................................... 17 4.1 analog inputs ............................................................................................................. ...... 17 4.2 voltage reference ......................................................................................................... .. 17 4.3 oscillator characteristics ................................................................................................ .17 4.4 calibration ............................................................................................................... ......... 17 4.4.1 overview of calibration process ...... ................................................................... 17 4.4.2 calibration sequence .......................................................................................... 18 4.4.3 calibration signal input level ............................................................................. 18 4.4.4 calibration signal frequency ........... ................................................................... 18 4.4.5 input configurations fo r calibrations ................................................................... 18 4.4.6 description of calibration algorithms .................................................................. 19 4.4.6.1 ac offset calibration sequence ......................................................... 19 4.4.6.2 dc offset calibration sequence ......................................................... 19 4.4.6.3 ac gain calibrati on sequence ........................................................... 19 4.4.6.4 dc gain calibration sequence ........................................................... 20 4.4.7 duration of calibration sequence .... ................................................................... 20 4.4.8 order of calibra tion sequences .......................................................................... 20 4.5 power offset .............................................................................................................. ...... 21 4.6 phase compensation ....................................................................................................... 2 1 4.7 time-base calibration ..................................................................................................... 21 4.8 on-chip temperature sensor .......................................................................................... 22 4.9 interrupt ................................................................................................................. .......... 22 4.9.1 typical use of the int pin ................................................................................... 22 4.9.2 int active state .................................................................................................. 22 4.10 voltage sag-detect feature .......................................................................................... 23 5. energy pulse outputs .................................................................................................. 24 5.1 pulse-rate output (eout and edir) ............................................................................. 24 5.2 pulse output for normal format, stepper motor format and mechanical counter format ............................................................................................................ 24 5.2.1 normal format .................................................................................................... 24 5.2.2 mechanical counter format ................................................................................ 25 5.2.3 stepper motor format ......................................................................................... 25 5.3 fout pulse output ......................................................................................................... 25 5.4 anti-creep for the pulse ou tputs ..................................................................................... 26 5.5 design examples ........................................................................................................... .. 26
cs5461 ds546pp2 3 5.6 auto-boot mode using eeprom .............. ................ ................ ................ ............. ......... 27 5.6.1 auto-boot configuration ...................................................................................... 27 5.6.2 auto-boot data for eeprom ........ ................ ................ ................ ............. ......... 28 5.6.3 which eeproms can be us ed? .............. ................ ................ ................ ......... 28 6. serial port overview .................................................................................................... 29 6.1 commands .................................................................................................................. .... 29 6.2 serial port interface ..................................................................................................... .... 32 6.3 serial read and write ..................................................................................................... 32 6.4 system initialization ..................................................................................................... .... 32 6.5 serial port initialization ................................................................................................ .... 33 6.6 cs5461 power states ..................................................................................................... 33 7. register description .................................................................................................... 34 7.1 configuration register ..................................................................................................... .34 7.2 dc current offset register and dc voltage offset register ........................................... 35 7.3 ac/dc current gain register and ac/dc voltage gain register ................................... 35 7.4 cycle count register....................................................................................................... .35 7.5 pulseratee register ........................................................................................................ 36 7.6 i, v, p, & pavg: instantaneous current, voltage, power, and average power (signed) output register............................................................................................................. 36 7.7 irms, vrms unsigned output register .......................................................................... 36 7.8 timebase calibration register ......................................................................................... 36 7.9 power offset register ...................................................................................................... 37 7.10 status register and mask register .......... ...................................................................... 37 7.11 ac current offset register and ac volt age offset register ......................................... 38 7.12 pulseratef register ...................................................................................................... 3 9 7.13 temperature sensor output register ............................................................................ 39 7.14 pulsewidth ................................................................................................................ ...... 39 7.15 vsaglevel: voltage sag-detect threshold level ........................................................ 39 7.16 vsagduration: voltage sag-detect durati on level...................................................... 40 7.17 control register.......................................................................................................... .... 40 8. basic application circuits .......................................................................................... 41 9. package dimensions ...................................................................................................... 44 10. revisions ............................................................................................................... ........... 45
cs5461 4 ds546pp2 list of figures figure 1. cs5461 read and write timing diagr ams .................................................................... 13 figure 2. data flow. ........................................................................................................... ........... 14 figure 3. oscillator connection ................................................................................................ ..... 17 figure 4. system calibration of gain. .......................................................................................... .18 figure 5. system calibration of offset. ........................................................................................ .18 figure 6. calibration data flow ................................................................................................ ..... 19 figure 7. example of ac gain calibration .................................................................................... 20 figure 8. another example of ac gain calibrati on....................................................................... 20 figure 9. example of dc gain calibration .................................................................................... 20 figure 10. time-plot representation of pulse outpu t for a typical burst of pulses (normal format)24 figure 11. mechanical counter fo rmat on eout and edir ........................................................ 25 figure 12. stepper moto r format on eout and edir ................................................................. 25 figure 13. typical interface of eeprom to cs5461 .... ................ ............. ............. ............. ......... 27 figure 14. typical connection diagram (one-phase 2-wire, direct connect to power line) ...... 41 figure 15. typical connection diagram (one-phase 2-wire, isolated from power line) ............. 42 figure 16. typical connection diagram (one-phas e 3-wire)....................................................... 42 figure 17. typical connection diagram (one-phase 3-wire - no neutral available)................... 43
cs5461 ds546pp2 5 1. general description the cs5461 is a cmos monolithic po wer measurement device with a re al power/energy computation en- gine. the cs5461 combines two progr ammable gain am plifiers, two ? modulators, two high rate filters, system calibration, and calculation f unctions to provide instantaneous voltage and current data samples and to calculate average (real) power, v rms , i rms , and instantaneous power data samples. the cs5461 functionality is optimized for power measur ement applications and is optimized to interface to a shunt or current tran sformer for current measurement, and to a resistive divider or potential transform- er for voltage measurement. to acco mmodate various input vol tage levels from a mu ltitude of current sen- sors, the cs5461?s current channel has a front-end pr ogrammable gain amplifier (pga), which allow for two available full-scale diff erential input signal ranges on the current channel: 100 mv p-p and 500 mv p-p , while the voltage channel ha s a set input range of 500 mv p-p . with single +5 v (common-mode) supply across va+/va-, both of the cs5461? s input channels can accommodate (common-mode + signal) levels between -0.25 v and va+. this allows for a completely bipolar differential i nput configuration. the com- mon-mode voltage level of the differential input signa ls can be anywhere between the supply voltage levels on the va+/va- pins, as long as enough voltage margin is left over so th at the addition of the differential signals will not cause the total swi ng to go below -0.25 v or above +5 v. the cs5461 includes two high-rate digital filters, which deci mate the output from the two ? modulators. these filters integrat e the output of the ? modulators for both channels to yield instantaneous voltage and current waveform output data at a (mclk/k)/1024 output word rate (owr). to facilitate communication to a mi crocontroller, the cs5461 includes a si mple three-wire serial interface which is spi? and microwire? compatible.
cs5461 6 ds546pp2 2. pin description vrefin 12 voltage reference input vrefout 11 voltage reference output vin- 10 differential voltage input vin+ 9 differential voltage input mode 8 mode select cs 7 chip select sdo 6 serial data ouput sclk 5 serial clock dgnd 4 digital ground vd+ 3 positive power supply cpuclk 2 cpu clock output xout 1 crystal out va- 13 analog ground va+ 14 positive analog supply iin- 15 differential current input iin+ 16 differential current input pfmon 17 power fail monitor fout 18 high frequency output reset 19 reset int 20 interrupt eout 21 energy output edir 22 energy direction indicator sdi 23 serial data input xin 24 crystal in clock generator crystal out crystal in 1,24 xout, xin - a gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. alternatively, an external (cmos compatible) clock can be supplied into xin pin to provide the system clock for the device. cpu clock output 2 cpuclk - output of on-chip oscillator which can drive one standard cmos load. control pins and serial data i/o serial clock input 5 sclk - a clock signal on this pin determines the input and output rate of the data for the sdi and sdo pins respectively. this is a schmit t trigger input to allow for slow rise time signals. the sclk pin will re cognize clocks only when cs is low. serial data output 6 sdo -the serial data port output pin. its out put is in a high impedance state when cs is high. chip select 7 cs - when low, the port will recognize sclk. an active high on this pin forces the sdo pin to a high impedance state. mode select 8 mode - when at logic high, the cs5461 will operate in auto-boot mode. for normal operation this pin must be left unconnected. high-frequency energy output 18 fout - issues active-low pulses, such that t he number of pulses is proportional to the measured real energy. the energy-to-pulse ra tio is programmed in the pulseratef reg- ister. reset 19 reset - when reset is taken low, all internal registers are set to their default states. interrupt 20 int - when int goes low it signals that an enabled event has occurred. energy output 21 eout - issues fixed-width pulses, such that the number of pulses is proportional to the real energy registration of the device. the energy-to-pulse ratio is programmed in the pulseratee register. energy direction indicator 22 edir - indicates if the measured energy is negative. serial data input 23 sdi - the serial data port input pin. data will be input at a rate determined by sclk.
cs5461 ds546pp2 7 measurement and reference input differential voltage inputs 9,10 vin+, vin- - differential analog input pins for the voltage channel. differential current inputs 15,16 iin+, iin- - differential analog input pins for the current channel. voltage reference output 11 vrefout - the on-chip voltage reference output. the voltage reference has a nominal magnitude of 2.5 v and is referenced to the va- pin on the converter. voltage reference input 12 vrefin - the input to this pin establishes the voltage reference for the on-chip modula- tor. power supply connections positive digital supply 3 vd+ - the positive digital supply relative to dgnd. digital ground 4 dgnd - the common-mode potential of digital ground must be equal to or above the common-mode potential of va-. positive analog supply 14 va+ - the positive analog supply relative to va-. analog ground 13 va- - the analog ground pin must be at the lowest potential. power fail monitor 1 7 pfmon - the power fail monitor pin monitors the analog supply. typical threshold level (pmlo) is 2.45 v with respect to the va- pin. if pfmon voltage threshold is tripped, the lsd (low-supply detect) bit is set in the status register. once the lsd bit has been set, it cannot be reset until the pfmon voltage in creases ~100 mv (typical) above the pmlo voltage.
cs5461 8 ds546pp2 3. characteristics /specifications ? min / max characteristics and specifications are gu aranteed over all operating conditions. ? typical characteristics and specifications are measured at nominal supply voltages and t a = 25c. ? dgnd = 0 v. all voltages with respect to 0 v. recommended operating conditions analog characteristics notes: 1. applies after system calibration 2. effective input impedance (eii) is determined by clock frequency (dclk) and input capacitance (ic). eii = 1/(ic*dclk/4). note that dclk = mclk / k. parameter symbol min typ max unit positive digital power supply vd 3.135 3.3 5.25 v positive analog power supply va+ 4.75 5 5.25 v negative analog power supply va- -0.25 0 0.25 v voltage reference vref - 2.5 - v specified temperature range t a -40 - +85 c parameter symbol min typ max unit accuracy (both channels) common mode rejection (dc, 50, 60 hz) cmrr 80 - - db offset drift (without the high pass filter) - 5 - nv/c analog inputs (current channel) differential input voltage range (gain = 10) {(iin+) - (iin-)} (gain = 50) iin 0 0 - - 500 100 mv p-p mv p-p total harmonic distortion thd 74 - - db common mode + signal all gain ranges -0.25 - va+ v crosstalk with voltage channel at full scale (50, 60 hz) - - -115 db input capacitance (gain = 10) (gain = 50) ic - - 25 25 - - pf pf effective input impedance (gain = 10) (note 2) (gain = 50) eii 30 30 - - - - k ? k ? noise (referred to input) (gain = 10) (gain = 50) n i - - - - 22.5 4.5 v rms v rms accuracy (current channel) bipolar offset error (note 1) vos - - 0.001 %f.s. full-scale error (note 1) fse - - 0.001 %f.s.
cs5461 ds546pp2 9 analog characteristics (continued) notes: 3. the minimum fscr is limited by the maximum allowed gain register value. parameter symbol min typ max unit analog inputs (voltage channel) differential input voltage range {(vin+) - (vin-)} vin 0 - 500 mv p-p total harmonic distortion thd 65 - - db common mode + signal all gain ranges -0.25 - va+ v crosstalk with current channel at full scale (50, 60 hz) - - -70 db input capacitance all gain ranges ic - 0.2 - pf effective input impedance (note 2) eii 5 - - m ? noise (referred to input) n v --250 v rms accuracy (voltage channel) bipolar offset error (no te 1) vos - - 0.01 %f.s. full-scale error (note 1) fse - - 0.01 %f.s. dynamic characteristics phase compensation range (voltage channel, 60 hz) -2.8 - +2.8 high rate filter output word ra te (both channels) owr - dclk/1024 - hz input sampling rate dclk = mclk/k - dclk/8 - hz full scale dc calibration range (note 3) fscr 25 - 100 %f.s. channel-to-channel time-shift error (when pc[6:0] bits are set to ?0000000?) 1.0 s high pass filter pole frequency -3 db - 0.5 - hz
cs5461 10 ds546pp2 analog characteristics (continued) notes: 4. the minimum fscr is limited by the maximum allowed gain register value. 5. all outputs unloaded. all inputs cmos level. 6. definition for psrr: vrefin tied to vrefout, va+ = vd+ = 5 v, a 150 mv (zero-to-peak) (60 hz) sinewave is imposed onto the +5 v dc supply voltage at va+ and vd+ pins. the ?+? and ?-? input pins of bot h input channels are shorted to va-. then the cs5461 is commanded to continuous conversion acquisition mode, and digital output data is collect ed for the channel under test. the (zero-to-peak) value of the d igital sinusoidal output signal is determined, and this value is c onverted into the (zero-to-peak) value of th e sinusoidal voltage (measured in mv) that would need to be applied at the channel?s inputs, in order to cause the same digital sinusoidal output. this voltage is then defined as v eq . psrr is then (in db): 7. when voltage level on pfmon is sagging, and lsd bit is at 0, the voltage at which lsd bit is set to 1. 8. if the lsd bit has been set to 1 (because pfmon volt age fell below pmlo), this is the voltage level on pfmon at which the lsd bit can be permanently reset back to 0. voltage reference notes: 9. the voltage at vrefout is measured across th e temperature range. from these measurements the following formula is used to calculate the vrefout temperature coefficient:. parameter symbol min typ max unit power supplies power supply currents (active state) i a+ i d+ (vd+ = 5 v) i d+ (vd+ = 3.3 v) psca pscd pscd - - - 1.3 2.9 1.7 - - - ma ma ma power consumption active state (vd+ = 5 v) (note 5) active state (vd+ = 3.3 v) stand-by state sleep state pc - - - - 21 11.6 6.75 10 30 - - - mw mw mw w power supply rejection ra tio (note 6) (gain = 10) current channel (50, 60 hz) (gain = 50) psrr psrr 56 70 - - - - db db power supply rejection ra tio (note 6) (gain = 10) voltage channel (50, 60 hz) psrr 45 - - db pfmon low-voltage trigger threshold (note 7) pmlo 2.3 2.45 - v pfmon high-voltage power-on trip point (note 8) pmhi - 2.55 2.7 v parameter symbol min typ max unit reference output output voltage refout 2.4 - 2.6 v temperature coefficient (note 9) tc - 25 60 ppm/c load regulation (output current 1 a source or sink) ? v r -610mv reference input input voltage range vrefin 2.4 2.5 2.6 v input capacitance - 4 - pf input cvf current - 25 - na psrr 20 150 v eq -------- - ?? ?? ?? log ? = (vrefout max - vrefout min ) vrefout avg ( ( 1 t a max - t a min ( ( 1.0 x 10 ( ( 6 tc vref =
cs5461 ds546pp2 11 5 v digital characteristics 3 v digital characteristics parameter symbol min typ max unit high-level input voltage all pins except xin and sclk and reset xin sclk and reset v ih 0.6 vd+ (vd+) - 0.5 0.8 vd+ - - - - - - v v v low-level input voltage all pins except xin and sclk and reset xin sclk and reset v il - - - - - - 0.8 1.5 0.2 vd+ v v v high-level output voltage i out = +5 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = -5 ma v ol --0.4v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf parameter symbol min typ max unit high-level input voltage all pins except xin and sclk and reset xin sclk and reset v ih 0.6 vd+ (vd+) - 0.5 0.8 vd+ - - - - - - v v v low-level input voltage all pins except xin and sclk and reset xin sclk and reset v il - - - - - - 0.48 0.3 0.2 vd+ v v v high-level output voltage i out = +5 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = -5 ma v ol --0.4v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf
cs5461 12 ds546pp2 switching characteristics notes: 10. device parameters are specif ied with a 4.096 mhz clock. if a crysta l is used, then xi n frequency must remain between 2.5 mhz - 5.0 mhz. if an external oscillator is us ed, full xin freq uency range is 2.5mhz-20mhz. 11. if external mclk is used, then its duty cycle must be between 45% and 55% to maintain this spec. 12. specified using 10% and 90% points on wave-form of interest. output loaded with 50 pf. 13. oscillator start-up time varies with crystal parameters. this specificat ion does not apply when using an external clock source. parameter symbol min typ max unit master clock frequency int ernal gate oscillator (n ote 10) mclk 2.5 4.096 20 mhz master clock duty cycle 40 - 60 % cpuclk duty cycle (note 11) 40 60 % rise times any digital input except sclk (note 12) sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times any digital input except sclk (note 12) sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xt al = 4.096 mhz (note 13) t ost -60-ms serial port timing serial clock frequency sclk - - 2 mhz serial clock pulse width high pulse width low t 1 t 2 200 200 - - - - ns ns sdi timing cs falling to sclk rising t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sdo timing cs falling to sdi driving t 7 -2050ns sclk falling to new data bit (hold time) t 8 -2050ns cs rising to sdo hi-z t 9 -2050ns auto-boot timing serial clock pulse width high pulse width low t 10 t 11 8 8 mclk mclk mode setup time to reset rising t 12 50 ns reset rising to cs falling t 13 48 mclk cs falling to sclk rising t 14 100 8 mclk sclk falling to cs rising t 15 16 mclk cs rising to driving mode low (to end auto-boot sequence). t 16 50 ns sdo guaranteed setup time to sclk rising t 17 100 ns
cs5461 ds546pp2 13 t 1 t 2 msb msb-1 lsb com m and tim e 8 sclks sync0 com m and sync0 com m and sync0 com m and msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb high byte mid byte low byte cs sdo sclk sdi t 7 t 8 t 9 t 1 t 2 t 3 t 4 t 5 t 6 msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb command time 8 sclks high byte mid byte low byte cs sclk sdi t 11 t 10 reset sdo sclk cs last 8 bits sdi mode stop bit d ata from e e p r o m t 17 t 4 t 5 t 15 t 16 t 8 t 14 t 13 t 12 (input) (input) (o u t p u t ) (o u t p u t ) (o u t p u t ) (input) sdi write timing (not to scale) sdo read timing (not to scale) figure 1. cs5461 read and write timing diagrams auto-boot sequence timing (not to scale)
cs5461 14 ds546pp2 3.1 theory of operation a computational flow diagram for the two data paths is shown in fig. 2. the analog waveforms at the voltage/current channel inputs are subject to the gains of the input pgas. these waveforms are then sampled by the delta-sigma modulators at a rate of (mclk/k) / 8. 3.1.1 high-rate digital low-pass filters the data is then low- pass filtered, to remove high-frequency noise from the modulator output. referring to figure 2, the high rate filters on both channels are implemented as fixed sinc 3 filters. also note from figure 2 th at the digital data on the voltage channel is subjecte d to a variable time-de- lay filter. the delay depe nds on the value of the seven phase compensation bits (see phase com- pensation ) set in the configuration register. 3.1.2 digital compensation filters the data from both channels is then passed through two 4th-order iir ?compens ation? filters, whose purpose is to correct (com pensate) for the magni- tude roll-off of the lo w-pass filtering operation. these filters ?re-flatten? the magnitude response of the i and v channels over the relevant frequency range, by correcting for the magnitude roll-off ef- fects that are induced onto the i and v signal spec- trums by the sinc 3 low-pass filter stages. 3.1.3 digital high-pass filters both channels provide an optional high-pass filter (?hpf? in figure 2) which can be engaged into the signal path, in order to re move the dc content from the current/voltage signa l before the rms/energy calculations are made. thes e filters are activated by enabling certain bits in th e configuration register. 3.1.4 gain and dc offset adjustment after the filtering, the in stantaneous voltage and current digital codes are bot h subjected to value ad- justments, based on the va lues in the dc offset registers (additive) and th e gain registers (multi- plicative). these register s are used for calibration of the device (see section 4.4, calibration ). after offset and gain, the data is available to the user by reading the instantaneous voltage and current registers. 3.1.5 average (real) power computation the digital instantaneous voltage and current data is then processed further. referring to figure 2, the instantaneous voltage/current data samples are multiplied together (one multiplication for each pair of voltage/current sa mples) to form instanta- neous power data. the inst antaneous power data is then averaged over n instantaneous conversions (n = value in cycle count re gister) to form the re- sult in the average power register. the average power can be multiplied by the time duration of the voltage ? sinc 3 + x v* gn x v * current sinc 3 + x i* gn x delay reg delay reg hpf configuration register * pc [ 6:0] bits x i* rms n v* rms n p * e e out dir ? hpf iir i * p * n - - i acoff * i dcoff * v acoff * v dcoff * n pga pga iir n n x pulseratee + n n + * denotes register name + + 4th-order 4th-order tbc * energy - to - pulse x pulseratef f out * * energy - to - pulse + p off * x - avg figure 2. data flow.
cs5461 ds546pp2 15 computation cycle, to gene rate a value for the accu- mulated real energy over the last computation cy- cle. 3.1.6 rms computations rms calculations are perf ormed on the instanta- neous voltage/current data and can be read from the rms voltage register a nd the rms current reg- ister. the results are computed once every compu- tation cycle. using n instantaneous current samples (i n ), the rms computations for the current (and likewise for voltage, using v n ) is performed using the formula: 3.2 performing measurements the cs5461 performs measurements of instanta- neous voltage, instantaneou s current, instantaneous power at an output word rate (sampling rate) of (mclk/k) / 1024. from th ese instantaneous sam- ples, average (real) power, i rms , and v rms are computed, using the most recent n instantaneous samples that were acqui red. all of the measure- ments/results are available as a percentage of full scale. the signed output format is a two?s comple- ment format, and the output data words represent a normalized value between -1 and +1. the un- signed data in the cs5461 output registers repre- sent normalized values between 0 and 1. a register value of 1 represents the maximum possible value. note that a value of 1.0 is never actually obtained, the true maximum register value is [(2^23 - 1) / (2^23)] = 0.999999880791. after each a/d conversion, the crdy bit will be asserted in the status register, and the int pin will also become active if the crdy bit is unmasked (in the mask register). the assertion of the crdy bit indicates that new in stantaneous samples have been collected. the unsigned v rms , i rms , and average power cal- culations are updated ev ery n conversions (which is known as 1 ? computation cycle ?) where n is the value in the cycle count register. at the end of each computation cycle, the drdy bit in the mask register will be set, and the int pin will become active if the drdy bit is unmasked. drdy is set only after each computation cycle has completed, whereas the crdy bit is asserted after each individual a/d conversion. when these bits are asserted, they must be cleared by the user be- fore they can be asserted again. if the cycle count register value (n) is set to 1, all output calculations are instantaneous, and drdy will indicate when instantaneous calculations ar e finished, just like the crdy bit. for the rms resu lts to be valid, the cy- cle-count register must be set to a value greater than 10. a computation cycle is derived from the master clock and its frequency is (mclk/k)/(1024*n). under default conditions with a 4.096 mhz clock at xin, instantaneous a/ d conversions for voltage, current, and power are pe rformed at a 4000 hz rate, whereas i rms , v rms , and energy calculations are performed at a 1 hz rate. 3.3 cs5461 linearity performance table 1 lists the range of input levels (as a percent- age of full-scale registra tion in the average power, irms, and vrms registers) over which the output linearity of the vrms, irms and average power register measurements are guaranteed to be within 0.1%. this linearity is gua ranteed for all four of the available full-scale input voltage ranges. n -1 n = 0 n i n rms = avg power vrms irms range (% of fs) 0.1% - 100% 1% - 100% 0.2% - 100% linearity 0.1% of reading 0.1% of reading 0.1% of reading table 1. available range of 0.1% output linearity, with default settings in the gain/offset registers.
cs5461 16 ds546pp2 note that until the cs5461 is calibrated (see cali- bration) the accuracy of the cs5461 (with respect to a reference line-voltage and line-current level on the power mains) is not guaranteed to within 0.1%. but the linearity of any given sample of cs5461, before calibration, wi ll be within 0.1% of reading over the ranges specified, with respect to the input voltage levels required to cause full-scale readings in the irms/vrm s registers. table 1 de- scribes linearity + variati on specs after the comple- tion of each successive computation cycle. the accuracy of the intern al calculations can often be improved by selecti ng a value for the cy- cle-count register that wi ll cause the time duration of one computation cycle to be equal (or very close to) a whole-number of power-line cycles (and n must be greater than or equal to 4000). for exam- ple, with the cycle count set to 4200, the 0.1% of reading linearity range fo r measurement of a 60 hz sinusoidal current-sense voltage signal can be in- creased beyond the range of 0.2% - 70.7%. the lin- earity range can be increased because (4200 samples / 60 hz) is a whol e number of cycles (70).
cs5461 ds546pp2 17 4. functional description 4.1 analog inputs the cs5461 has two availabl e full-scale differen- tial input voltage ranges on the current channel and one full-scale differential input voltage range on the voltage channel. the input ranges are the maximum sinusoidal sig- nals that can be applied to the current and voltage channels, yet these values will not result in full scale registration in the instantaneous current and voltage registers. if the current and volta ge channels are set to 500 mv p-p , only a 250 mv rms signal will register full scale. yet it would not be practical to inject a sinusoidal signal with a value of 250 mv rms . when such a sine wave enters the higher levels of its positive crest region ( over each cycle), the volt- age level of this signal exceeds the maximum dif- ferential input voltage rang e of the input channels. the largest sine wave vol tage signal that can be placed across the inputs, with no saturation is: which is ~70.7% of full-scal e. so for sinusoidal in- puts at the full scale peak-to-peak level the full scale registration is ~.707. 4.2 voltage reference the cs5461 is specified for operation with a +2.5 v reference between the vrefin and va- pins. the converter include s an internal 2.5 v ref- erence (60 ppm/c drift) that can be used by con- necting the vrefout pin to the vrefin pin of the device. if higher accuracy/stability is required, an external reference can be used. 4.3 oscillator characteristics xin and xout are the input and output of an in- verting amplifier to provi de oscillation and can be configured as an on-chip oscillator, as shown in figure 3. the oscillator ci rcuit is designed to work with a quartz crystal or a ceramic resonator. to re- duce circuit cost, two load capacitors c1 and c2 are integrated in the device. with these load capacitors, the oscillator circuit is capable of oscillation up to 20 mhz. to drive the de vice from an external clock source, xout should be left unconnected while xin is driven by the external circuitry. there is an amplifier between xi n and the digital section which provides cmos level signals. this amplifier works with sinusoidal i nputs so there are no prob- lems with slow edge times. the cs5461 can be driven by an external oscillator ranging from 2.5 to 20 mhz, but the k divider val- ue must be set such that the internal dclk will run somewhere between 2.5 mhz and 5 mhz. the k divider value is set with the k[3:0] bits in the con- figuration register. as an example, if xin = mclk = 15 mhz, and k is set to 5, then dclk is 3 mhz, which is a valid value for dclk. 4.4 calibration 4.4.1 overview of calibration process the cs5461 offers digita l calibration for both channels; ac/dc offset and ac/dc gain. for both 2 2 500mv p-p = ~176.78mv rms oscillator circuit dgnd xin xout c1 c1 = 22 pf c2 c2 = figure 3. oscillator connection
cs5461 18 ds546pp2 the voltage channel and th e current channel, the ac offset calibration sequenc e performs an entirely different function than the dc offset calibration se- quence. the ac gain and dc gain calibration se- quences perform the same function, but accomplish the function using different techniques. since both the voltage and current channels have separate offset and gain registers associated with them, system offset or system gain can be per- formed on either channel without the calibration results from one channe l affecting the other. 4.4.2 calibration sequence 1. before calibration th e cs5461 must be operat- ing in its active state, and ready to accept valid commands. the ?drdy? bit in the status register should also be cleared. 2. apply appropriate calibr ation signals to the in- puts of the voltage/current channels (discussed next in sections 4.4.3 and 4.4.4.) 3. send the 8-bit calibra tion command to the cs5461 serial interface. va rious bits within this command specify the exact type of calibration. 4. after the cs5461 finishes the desired internal calibration sequence, the drdy bit is set in the status register to indicat e that the calibration se- quence is complete. the results of the calibration are now available in the appropriate gain/offset registers. 4.4.3 calibration signal input level for ac/dc gain calibrations, there is an absolute limit on the rms/dc voltage levels that are select- ed for the gain calibrati on input signals. the maxi- mum value that the gain register can attain is 4. therefore, for either channe l, if the voltage level of a gain calibration input si gnal is low enough that it causes the cs5461 to attempt to set either gain reg- ister higher than 4, the gain calibration result will be invalid and all cs5461 results obtained while running a/d conversions will be invalid. 4.4.4 calibration si gnal frequency optimally, the frequency of the calibration signal is the same frequency as th e fundamental power line frequency of the metered power system. 4.4.5 input configurations for calibrations figure 4 shows the basic setup for gain calibration. when performing a dc gain calibration a positive dc voltage level must be applied at the inputs of the voltage/current channe ls. this voltage should be set to the level that represents the absolute max- imum instantaneous voltage level that needs to be measured across the input s (including the maxi- mum over-range level that must be accurately mea- sured). when performing ac gain calibration, an ac reference signal should be applied that repre- sents the desired maximum rms level. a typical sinusoidal calibration value which allows for rea- sonable over-range margin would be 0.6 or 60% of the voltage/current cha nnel?s maximum input volt- age level. for both ac and dc offset calibrations, the ?+? and ?-? pins of the voltage /current channels should + - xgain + - external connections + - ain+ ain- cm + - full scale (dc or ac) figure 4. system calibration of gain. + - xgain + - external connections 0v + - ain+ ain- cm + - figure 5. system calibration of offset.
cs5461 ds546pp2 19 be connected to their gr ound reference level. (see figure 5.) if offset and gain calibra tion command bits are set, only the offset calibration will be performed. 4.4.6 description of calibration algorithms the computational flow of the cs5461?s ac and dc gain/offset calibration sequences are illustrated in figure 6. this figure a pplies to both the voltage channel and the current channel. note: for proper ac calibration, the value of the voltage/current gain registers must be set to default (1.0) before running the gain calibration(s), and the value in the ac offset registers must be set to default (0) before running calibrations. this can be accomplished by a software or hardware reset of the device. the values in the voltage/current calibration registers do affect the results of the calibration sequences. 4.4.6.1 ac offset calibration sequence the ac offset calibration obtains an offset value that reflects the rms out put level when the inputs are grounded. during norma l operation, this ac offset register value will be subtracted from each successive voltage/current sample in order to nulli- fy the ac offset that may be inherent in the signal path. 4.4.6.2 dc offset calibration sequence the dc offset registers hold the negative of the simple average of n sa mples taken while the dc offset calibration was ex ecuted. the inputs should be grounded during dc offset calibration. the dc offset value is added to th e signal path to nullify the dc offset in the system. 4.4.6.3 ac gain calibration sequence the ac gain calibration al gorithm attempts to ad- just the gain register va lue such that the calibra- tion reference signal level presented at the voltage inputs will result in a value of 0.6 in the rms volt- age register. the rms level of the calibration signal must be determined by the user. during ac voltage gain calibration, the va lue in the rms voltage register is divided into 0.6 and stored in the volt- age gain register. two examples of ac calib ration and the resulting shift in the digital output codes of the channel?s in- stantaneous data register s are shown in figures 7 and 8. figure 8 shows that a positive (or negative) dc level signal can be used even though an ac gain calibration is being executed. however, an ac signal cannot be used for dc gain calibration. in modulator + x to v*, i*, p*, e* registers filter n v rms n sinc dc offset* gain* + x 2 -x 1 x n ac offset* x 2 0.6 x + + - + 2 * * denotes readable/writable register x n figure 6. calibration data flow
cs5461 20 ds546pp2 4.4.6.4 dc gain calibration sequence based on the level of the positive dc calibration voltage applied across the ?+? and ?-? inputs, the cs5461 determines the dc gain register value by averaging the instantaneous register?s output sig- nal values over one comput ation cycle (n samples) and then dividing this aver age into 1. therefore, af- ter the dc gain calibratio n, the instantaneous reg- ister will read at full-s cale whenever the dc level of the input signal is equa l to the level of the dc calibration signal applied to the inputs during the dc gain calibration (see figure 9). 4.4.7 duration of calibration sequence the value of the cycle count register (n) deter- mines the number of conve rsions performed by the cs5461 during a given cali bration sequence. for dc offset/gain calibrati ons, the calibration se- quence takes at least n + 30 conversion cycles to complete. for ac offset/gain calibrations, the cali- bration sequence takes at least 6n + 30 a/d con- version cycles to complete, (about 6 computation cycles). as n is increase d, the accuracy of calibra- tion results will increase. 4.4.8 order of calibration sequences 1. if the measured signal needs to include any dc content that may be present in the voltage/current and power/energy signals, run dc offset calibra- tion first. however, if the hpf options are turned on, then any dc component that may be present in v rms register = 230 / 250 x 1 / 2 0.65054 250 mv 230 mv 0 v -230 mv -250 mv 0.9999... 0.92 -0.92 -1.0000... v rms register = 0.6000... 250 mv 230 mv 0 v -230 mv -250 mv 0.84853 -0.84853 before ac gain calibration (vgain register = 1) after ac gain calibration (vgain register changed to ~0.9223) instantaneous voltage register values instantaneous voltage register values sinewave sinewave 0.92231 -0.92231 input signal input signal figure 7. example of ac gain calibration v rms register = 230 / 250 = 0.92 250 mv 230 mv 0 v -250 mv 0.9999... 0.92 -1.0000... v rms register = 0.6000... 250 mv 230 mv 0 v -250 mv 0.6000 before ac gain calibration (vgain register = 1) after ac gain calibration (vgain register changed to ~0.65217) instantaneous voltage register values instantaneous voltage register values dc signal dc signal 0.65217 -0.65217 input signal input signal figure 8. another exampl e of ac gain calibration v rms register = 230 / 250 = 0.92 250 mv 230 mv 0 v -250 mv 0.9999... 0.92 -1.0000... v rms register = 0.9999... 230 mv 0 v 0.9999... before dc gain calibration (vgain register = 1) after dc gain calibration (vgain register changed to 1.0870) instantaneous voltage register values instantaneous voltage register values dc signal dc signal input signal input signal figure 9. example of dc gain calibration
cs5461 ds546pp2 21 the power/energy signals wi ll be removed from the cs5461?s power/energy results. 2. if the energy registrati on accuracy needs to be within 0.1% (with respect to reference calibration levels on the voltage/current inputs) then either the ac or the dc gain calib ration is recommended for the voltage/current channels. 3. finally, run ac offset calibration on the voltage and current channels. 4.5 power offset the power offset register can be used to offset system power sources that may be resident in the system, but do not origin ate from the power line signal. these sources of extra energy in the system contribute undesirable and fa lse offsets to the pow- er/energy measurement results. after determining the amount of stray power, the power offset reg- ister can be set to nullify the effects of this unwant- ed energy. 4.6 phase compensation bits 23 to 17 of the conf iguration register are used to program the amount of phase delay added to the voltage channel si gnal path. this phase delay is ap- plied to the voltage channe l signal in order to com- pensate for phase delay that may be introduced by the voltage and current sens or circuitry external to the cs5461. voltage and current transformers, as well as other sensor e quipment applied to the front-end of the cs5461 input s can often introduce a phase delay in the syst em, which distorts the phase relationship between the voltage and current signals being measured. the phase compensation bits pc[6:0] can be set to nullify this undesirable phase distortion between the two channels. the default value of the phase compensation bits is 0000000(b). this setting re presents the shortest time-delay (smallest phase delay) between the volt- age and current channel si gnal paths. with the de- fault setting, the phase delay on the voltage channel is 0.995 s (~0.0215 degrees assuming a 60 hz power signal). with mclk = 4.096 mhz and k = 1, the range of the internal phase compensation ranges from -2.8 degrees to +2.8 degrees when the input voltage/curre nt signals are at 60 hz. in this condition, each step of th e phase compensation reg- ister (value of one lsb) is ~0.04 degrees. for val- ues of mclk other than 4.096 mhz, the range (-2.8 to +2.8 degrees) a nd step size (0.04 degrees) should be scaled by 4.096 mhz / (mclk / k). for power line frequencies ot her than 60 hz, the values of the range and step size of the pc[6:0] bits can be determined by converting the above values to time-domain (seconds), and then computing the new range and step size (i n degrees) with respect to the new line frequency. to calibrate the phase de lay, use a purely resistive load and adjust the phase compensation bits until the average power register value is maximized. 4.7 time-base calibration the time-base calibration register (notated as ?tbc? in figure 2) is used to compensate for slight errors in the xin frequency. external oscillators and crystals have certain tolerances. to improve the accuracy of the clock for energy measurements, the time-base calibration register can be manip- ulated to compensate for the frequency error. note from figure 2 that the t bc register only affects the value in the average power register. as an example, if the desired xin frequency is 4.096 mhz, but during production-level testing the average frequency of the crystal on a particular board is measured to be 4.091 mhz. the ratio of the desired frequency to the actual frequency is 4.096 mhz / 4.091 mhz = ~1.00122219506. the time-base calibration re gister can be set to 1.00122213364 = 0x80280c(h), which is close to the desired ratio.
cs5461 22 ds546pp2 4.8 on-chip temperature sensor after a few minutes of normal-active operation in ?continuous conversions? data acquisition mode, the cs5461 will stabilize to a constant steady-state operating temperature. however, the cs5461?s op- erating temperature may be influenced by changes in the ambient temperature. such ambient temper- ature fluctuations will cause some drift in the gain of the cs5461?s two a/d converters. the on-chip temperature sensor provide s the option to calibrate such drift. the output code value in the temperature register is the relative temperat ure reading of the on-chip temperature sensor. by recording the digitized temperature readings and comparing these readings to the fluctuations in the a/d output codes of the vrms and irms regis- ter readings, the fluctuat ion of the a/d converter can be characterized over a wide range of ambient temperatures. once a temperature drift ch aracterization of the de- vice has been performed, a temperature compensa- tion algorithm can be inte grated into the firmware within the on-board mcu to compensate for this temperature drift. 4.9 interrupt the int pin is used to indicate that an event has taken place in the converter that needs attention. these events inform th e system about operation conditions and internal error conditions. the int signal is created by combining the status register with the mask register. wh enever a bit in the sta- tus register becomes activ e, and the corresponding bit in the mask register is a logic 1, the int signal becomes active. the inte rrupt condition is cleared when the bits of the status register are returned to their inactive state. 4.9.1 typical use of the int pin the steps below show how interrupts can be han- dled. ? initialization : step i0 - all status b its are cleared by writing ffffff (hex) into the status register. step i1 - the conditional bits which will be used to generate interrupts are then set to logic 1 in the mask register. step i3 - enable interrupts. ? interrupt handler routine : step h0 - read the status register. step h1 - disable all interrupts. step h2 - branch to the proper interrupt service routine. step h3 - clear the status register by writing back the read value in step h0. step h4 - re-enable interrupts. step h5 - return from interrupt service routine. this handshaking proce dure insures that any new interrupts activated between steps h0 and h3 are not lost (cleared) by step h3. 4.9.2 int active state the behavior of the int pin is controlled by the imode and iinv bits of the configuration regis- ter. the pin can be active low (default), active high, active on a return to logi c 0 (pulse-low), or active on a return to logic 1 (pul se-high). if the interrupt output signal format is se t for either pulse-high or pulse-low, the dura tion of the int pulse will be at least one dclk cycle (dclk = mclk / k).
cs5461 ds546pp2 23 4.10 voltage sag-detect feature the cs5461 includes status register bit, vsag; which indicates a sag in the power line voltage. in order for sag condition to be identified, the mea- sured v rms must remain below a set sag threshold level for a specified period of time. to activate this feature, a voltage threshold value must be specified in the voltage sag level register (vsag level ); and a time-durati on must be specified in the voltage sag duration register (vsag dura- tion ). this time duration is specified in terms of a/d cycles. if v rms is measured below the level specified in the vsag level register for a durat ion of time great- er than or equal to th e number of a/d conversions specified in the vsag duration register, then the vsag bit in the status re gister will be asserted.
cs5461 24 ds546pp2 5. energy pulse outputs 5.1 pulse-rate output (eout and edir ) eout and edir pins provide pulses which repre- sent a predetermined ma gnitude of energy. with mclk = 4.096 mhz, and de fault settings, the pulses will have an averag e frequency equal to the frequency setting in the pulseratee register when the input signals into the voltage and current chan- nels cause full-scale read ings in the instantaneous voltage and current registers. when mclk/k is not equal to 4.096 mhz, th e user should scale the pulse-rate by a factor of 4.096 mhz / (mclk / k) to get the actual output pulse-rate. 5.2 pulse output for normal format, stepper motor format and mechanical counter format eout and edir pins can be set in three different output formats. the default setting is normal output pulse format. when the pulse is set to either of the other two formats, the time duration and/or the rel- ative timing of the eout and edir pulses is var- ied such that the pulse s can drive either an electro-mechanical counter or a stepper motor. the ability to set the pulse out put format to one of the three available formats is controlled by setting cer- tain bits in the control register. 5.2.1 normal format in normal format the eout and edir pulse out- put format is illustrate d in figure 10. these are ac- tive-low pulses of short duration. a positive energy pulse is represented by a pulse on the eout pin while the edir will remain high. a negative ener- gy pulse is represente d by synchronous pulses on both the eout pin and the edir pin. the pulse duration is an integer multiple of mclk cycles, approximately equal to 1/16 of the period of the contents of the puls e-rate register. however for pulse-rate register se ttings less than the sam- pling rate (which is [m clk/8]/1024), the pulse du- ration remains constant and is equal to the duration of the pulses when the puls e-rate register is set to [mclk/k]/1024. the maxi mum pulse frequency from the eout pin is therefore [mclk / k] / 8. when dclk is not equal to 4.096 mhz, the pulse duration can be predicte d by using the pulse dura- tion values in table rr and dividing them by (mclk/k) / 4.096 mhz. in normal pulse output fo rmat, the number of puls- es depends on the value of the pulseratee register and on the amount of energy registered over the most recent a/d sampling period. a running total of the energy accumulation is maintained in an in- ternal register inside the cs5461 (not available to the user). after each a/d conversion cycle, the re- sult in the power register is multiplied by the value in the pulseratee register , and also by the value in the tbc (time-base cali bration) register, and then added to this internal energy accumulation register. once a certain am ount of positive or neg- eout edir t positive energy burst negative energy burst . . . . . . . . . . . . figure 10. time-plot repres entation of pulse output for a typi cal burst of pulses (normal format)
cs5461 ds546pp2 25 ative energy accumulation is reached in this regis- ter, the cs5461 will i ssue either a positive or negative energy pulse on the eout /edir pins. after the pulse or pulses ar e issued, a certain resid- ual amount of energy may be left over in this inter- nal energy accumulation regi ster. in this situation, the residual energy is not lost or discarded, but rath- er it is maintained and added to the energy that is accumulated during th e next update period. 5.2.2 mechanical counter format setting the mech bit in th e control register to ?1? and the step bit to ?0? enables wide-stepping puls- es for mechanical count ers and similar discrete counter instruments. in default mechanical mode format, active-low pulses are 128 ms wide when using a 4.096 mhz crystal and k = 1. when energy is positive, the pulses appear on eout . when en- ergy is negative, pulses appear on edir (see fig- ure 11). the pulse width is set in the pulsewidth register and will limit th e pulse frequency avail- able. it is up to the user to insure that pulses will not occur at a rate faster than the 128 ms pulse dura- tion, or faster than the me chanical counter can ac- commodate. this is done by verifying that the pulseratee register is se t to an appropriate value. because in the default state the duration of each pulse is set to 128 ms, the maximum output pulse frequency is limite d to ~7.8 hz (for mclk/k = 4.096 mhz). for values of mclk/k different than 4.096 mhz, the duration of one pulse is (128*4.096 mhz)/(mclk/k) milliseconds. 5.2.3 stepper motor format setting the step bit in the control register to ?1? and the mech bit to ?0? transforms the eout and edir pins into two-phase stepper motor outputs. when an energy pulse o ccurs, one of the outputs changes state. when the next energy pulse occurs, the other output changes st ate. the direction the motor will rotate is dete rmined by the order of the state changes. when energy is positive, eout will lead edir . when energy is negative, edir will lead eout (see figure 12). 5.3 fout pulse output in many metering applicati ons, the pulse frequency to power rate on the eout pin may be set to a rel- atively low value, such that the pulse frequency is on the order of 1-100 hz at nominal power con- sumption levels. however, calibration can take a long time at such output frequencies. in order to re- duce the time needed to verify the meter an extra pulse frequency-to-power output is provided on the fout pin. the pulse frequency-to-power rate can 128 ms 128 ms eout edir positive energy negative energy ... ... ... ... figure 11. mechanical co unter format on eout and edir eout edir positive energy negative energy ... ... ... ... figure 12. stepper motor format on eout and edir
cs5461 26 ds546pp2 be set to a value much higher than the eout pulse rate. the fout pin outputs negative and positive ener- gy, but has no energy direct ion indicator. the max- imum fout pulse frequency is set by the value in the pulseratef register. 5.4 anti-creep for the pulse outputs anti-creep can be enab led/disabled for both eout /edir and fout pulse output systems in the control register. anti -creep allows the elec- tronic meter to maintain a ?buffer? energy band, defined by positive/negati ve energy threshold lev- els, such that when the magnitude of the accumu- lated energy is below this level, no energy pulses are issued. the anti-creep feature is especially use- ful when the meter demands that the energy pulse outputs are set to relative ly high frequency. a high- er frequency pulse rate m eans that less energy reg- istration is required to gene rate a pulse; and so it is more likely that random noise present in the power line and/or current-sense circuit can generate a pulse that does not represent billable energy. 5.5 design examples example #1: for a power line with maximum rated levels of 250 v (rms) and 20 a (rms), the pulse-frequency on the eout pin needs to be ?ir? = 100 pulses-per-second (100 hz) when the rms-voltage and rms-curr ent levels on the power line are 220 v and 15 a respectively. to meet this requirement, the pulse-rate frequency (?pr?) in the pulse-rate register mu st be set accordingly. after calibration, the first step to finding the value of ?pr? is to set the volta ge and current sensor gain constants, k v and k i , such that there will be accept- able voltage levels on the cs5461 inputs when the power line voltage and cu rrent levels are at the maximum values of 250 v and 20 a. k v and k i are needed to determine the a ppropriate ratios of the voltage/current transforme rs and/or shunt resistor values to use in the fr ont-end voltage/current sen- sor networks. for a sinewave, the larges t rms value that can be accurately measured (wit hout over-driving the in- puts) will register ~0.707 of the maximum dc in- put level. since powe r signals are often not perfectly sinusoidal in real -world situations, and to provide for some over-range capability, the rms voltage register and rms current register is set to measure 0.6 when th e rms-values of the line-voltage and line-curr ent levels are 250 v and 20 a. therefore, when th e rms registers measure 0.6, the voltage level at the inputs will be 0.6 x 250 mv = 150 mv. the sensor gain con- stants, k v and k i , are determined by demanding that the voltage and curr ent channel inputs should be 150 mv rms when the power line voltage and current are at the maximum values of 250 v and 20 a. k v = 150 mv / 250 v = 0.0006 k i = 150 mv / 20 a = 0.0075 ? these sensor gain constants are used to calculate what the input voltage levels will be on the cs5461 inputs when the line-volta ge and line-current are 220 v and 15 a. these values are v vnom and v in- om. v vnom =k v * 220 v = 132 mv v inom =k i * 15 a = 112.5 mv the pulse rate on eout will be at ?pr? pulses per second (hz) when the rms- levels of voltage/cur- rent inputs are at 250 mv . when the voltage/cur- rent inputs are set at v vnom and v inom , the pulse rate needs to be ?ir? = 100 pulses per second. ir will be some percentage of pr. the percentage is defined by the ratios of v vnom /250 mv and v inom /250 mv with the following formula: pulserate ir pr v vnom 250mv ------------------- v inom 250mv ------------------- ?? ==
cs5461 ds546pp2 27 from this equation the valu e of ?pr? is shown as: therefore the pulse-rate register is set to ~420.875 hz, or 0x00349c. example #2 : the required numbe r of pulses per unit energy present at eout is specified to be 500 pulses/kw-hr; given that the maximum line-voltage is 250 v (rms) and the maximum line-current is 20 a (rms). in such a situation, the nominal line voltage and current do not determine the appropriate pulse-rate setting. instead, the max- imum line levels must be considered. as before, the given maximum line-voltage and line-current lev- els are used to determine k v and k i : k v = 150 mv / 250 v = 0.0006 k i = 150 mv / 20 a = 0.0075 ? again the sensor gains are calculated such that the maximum line-voltage and line-current levels will measure as 0.6 in the rm s voltage register and rms current register. with voltage and current channel input ranges set to 10x, the required pulse-rate register setting is determined using the following equation: therefore pr = ~1.929 hz. note that the pulse-rate re gister cannot be set to a frequency of exactly 1.929 hz. the closest setting that the pulse-rate register can obtain is 0x00003e = 1.9375 hz. to improve the accuracy, either gain register can be programmed to correct for the round-off error in pr. this value would be calculated as when mclk/k is not e qual to 4.096 mhz, the re- sult for ?pr? that is calculated for the pulse-rate register must be scaled by a correction factor of: 4.096 mhz / (mclk/k). for mclk/k of 3.05856 mhz the result is scaled by 4.096/3.05856 to get a final pr result of ~2.583 hz. 5.6 auto-boot mode using eeprom when the cs5461 mode pin is left unconnected, the cs5461 is in normal operating mode, called host mode . when this pin is set to logic high, the cs5461 auto-boot mode is enabled. in auto-boot mode, the cs5461 is confi gured to request a mem- ory download from an external serial eeprom. auto-boot mode allows the cs5461 to operate without the need for a microcontroller. 5.6.1 auto-boot configuration figure 13 shows the typical connections between the cs5461 and a serial eeprom for proper au- to-boot operation. in this mode, cs and sclk are driven outputs. during the auto-boot sequence, the cs5461 drives cs low, provides a clock output on sclk, and drives out-com mands on sdo. it re- ceives the eeprom data on sdi. the serial ee- prom must be pr ogrammed with the user-specified commands a nd register data that will be used by the cs5461 to change any of the default register values and begin conversions. pr ir v vnom 250mv ------------------ v inom 250mv ------------------ ------------------------------------------- - 100hz 132mv 250mv ------------------ 112.5mv 250mv ---------------------- - ------------------------------------------------ == pr 500 pulses kw hr ? ------------------ 1hr 3600s -------------- 1kw 1000w ----------------- - 250mv k v ------------------ 250mv k i ------------------ ?? ? ? = ign or vgn pr 1.929 ------------- 1.00441 ? 0x404830 == cs5461 eeprom /eout /edir mode sck sdi sdo /cs sck so si /cs connector to calibrator vd+ 5 k 5 k mech. counter stepper motor or figure 13. typical interf ace of eeprom to cs5461
cs5461 28 ds546pp2 figure 13 also shows the external connections that would be made to a calibr ator device, such as a pc or custom calibration boa rd. when the metering system is installed, the ca librator would be used to control calibration and/or to program user-speci- fied commands and calibration values into the ee- prom. the user-specifi ed commands/data will determine the cs5461?s exact operation, when the auto-boot initialization sequence is running. any of the valid commands can be used. 5.6.2 auto-boot data for eeprom below is an example code set for an auto-boot se- quence. this code is wr itten into the eeprom by the user. the serial data for such a sequence is shown below in single-byte hexidecimal notation: 40 00 00 61 ;in configuration register, turn high-pass filters on, set k=1. 44 7f c4 a9 ;write value of 0x7fc4a9 to current gain register. 46 7f b2 53 ;write value of 0xffb253 to dc voltage offset register. 4c 00 00 14 ;set pulseratee register to 0.625 hz. 74 00 00 04 ;unmask bit #2 (?lsd? bit in the mask register). e8 ;start continuous conversions 78 00 01 40 ;write stop bit to control register, to terminate au- to-boot initialization se- quence, and set the eout pulse output to mechanical counter format. 5.6.3 which eeproms can be used? several industry-standard serial eeproms that will successfully run auto-boot with the cs5461 are listed below: ? atmel at25010 at25020 at25040 ? national semiconductor nm25c040m8 nm25020m8 ? xicor x25040si these types of serial ee proms expect a specific 8-bit command word ( 00000011) in order to per- form a memory downloa d. the cs5461 has been hardware programmed to tr ansmit this 8-bit com- mand word to the eeprom at the beginning of the auto-boot sequence.
cs5461 ds546pp2 29 6. serial port overview the cs5461's serial port incorporates a state machine with transmit/rece ive buffers. the state machine in- terprets 8 bit command words on the rising edge of sclk. upon decoding of the command word, the state machine performs the requested command or prepares fo r a data transfer of the addressed register. request for a read requires an internal regist er transfer to the tran smit buffer, while a writ e waits until the comple- tion of 24 sclks before perfo rming a transfer. the internal register s are used to control the adc's func- tions. all registers are 24-bits in length. the cs5461 is initialized an d fully operational in its active state upon power-on. af ter a power-on, the device will wait to receive a valid command (the first 8-bits clocked into the serial port). upon receiving and decoding a valid command word, th e state machine instructs the conve rter to either perform a system operation, or transfer data to or from an internal register. 6.1 commands all command words are 1 byte in length. any 8-bit word that is not listed in this section is considered an invalid com- mand word. commands that write to a register must be follo wed by 3 bytes of register data. commands that read data can be chained with other commands (e.g., while read ing data, a new command can be sent to sdi which can execute before the original read is completed). 6.1.1 start conversions this command indicates to the state machine to begin acqui ring measurements and calculating results. the device has two modes of acquisition. c = modes of acquisition/measurement 0 = perform a single computation cycle 1 = perform continuou s computation cycles 6.1.2 sync0 command this command is the end of the serial port re-initializ ation sequence. the command can also be used as a nop command. the serial port is resynchronized to byte b oundaries by sending three or more consecutive sync1 com- mands followed by a sync0 command. 6.1.3 sync1 command this command is part of the serial port re-initializat ion sequence. the command also serves as a nop command. b7 b6 b5 b4 b3 b2 b1 b0 1110c000 b7 b6 b5 b4 b3 b2 b1 b0 11111110 b7 b6 b5 b4 b3 b2 b1 b0 11111111
cs5461 30 ds546pp2 6.1.4 power-up/halt if the device is powered-down, this command will initiate a pow er on reset. if th e part is already powered-on, all com- putations will be halted. 6.1.5 power-down and software reset the device has two power-down st ates to conserve power. if the chip is put in stand-by state, all circuitry except the analog/digital clock generators is turned of f. in the sleep state, all circuitry ex cept the digital clock generator and the instruction decoder is turned off. bringing the cs5461 ou t of sleep state requires more time than out of stand-by state, because of the extra time needed to re -start and re-stabilize the analog clock signal. s1,s0 power-down state 00 = software reset 01 = halt and enter stand-by power saving state. this state allows quick power-on time 10 = halt and enter sleep power saving stat e. this state requires a slow power-on time 11 = reserved 6.1.6 calibration the device can perform a system ac offset calibration, dc offset calibration, ac gain calibration, and dc gain cal- ibration. offset and gain calibrations should not be perfor med at the same time (must do one after the other). only one gain calibration sequence should be performed for any gi ven application. if calibration is needed, calibrate either ac gain or dc gain, but not both. the user must supply th e proper inputs to the device before initiating calibration. v,i designates calibration channel 00 = calibrate neither channel 01 = calibrate th e current channel 10 = calibrate the voltage channel 11 = calibrate voltage and current channel simultaneously r designates calibration 0 = dc calibration 1 = ac calibration g designates gain calibration 0 = no gain calibration 1 = perform gain calibration o* designates offset calibration 0 = no offset calibration 1 = perform offset calibration *if o is set then g is ignored. b7 b6 b5 b4 b3 b2 b1 b0 10100000 b7 b6 b5 b4 b3 b2 b1 b0 100s1s0000 b7 b6 b5 b4 b3 b2 b1 b0 110virgo
cs5461 ds546pp2 31 6.1.7 register read/write the read/write informs the state machine that a register access is required. during a read operation, the addressed register is loaded into the device?s outp ut buffer and clocked out by sclk. during a write operation, the data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24 th sclk. w/r write/read control 0 = read register 1 = write register ra[4:0] register address bits (bits 1 through 5) of the read/write command. address ra[4-0] abbreviation name/description 0 00000 config configuration register 1 00001 i dcoff current offset register 2 00010 i gn current gain register 3 00011 v dcoff voltage offset register 4 00100 v gn voltage gain register 5 00101 cycle count number of a/d conversions used in one computation cycle (n)). 6 00110 pulseratee sets the eout /edir energy-to-frequency output pulse rate. 7 00111 i instantaneous current register (last current value) 8 01000 v instantaneous voltage register (last voltage value) 9 01001 p instantaneous power register (last power value) 10 01010 p avg average power register (avg. powe r over last computation cycle) 11 01011 i rms rms current register (rms value over last comp. cycle) 12 01100 v rms rms voltage register (rms value over last comp. cycle) 13 01101 tbc timebase calibration register 14 01110 p off power offset calib ration register 15 01111 status status register (write of ?1? to status bit will clear the bit.) 16 10000 i acoff ac (rms) current offset register 17 10001 v acoff ac (rms) voltage offset register 18 10010 pulseratef sets the fout power-to-frequency output pulse rate. 19 10011 t temperature register 20 10100 res reserved ? 21 10101 pw pulse width register for mechanical counter output mode 22 10110 res reserved ? 23 10111 vsag level voltage sag level threshold register. 24 11000 vsag duration voltage sag duration register. 25 11001 res reserved ? 26 11010 mask mask register 27 11011 res reserved ? 28 11100 ctrl control register 29 11101 res reserved ? 30 11110 res reserved ? 31 11111 res reserved ? ? these registers are for internal use only. fo r proper device operation, the user must not attempt to write to these registers. b7 b6 b5 b4 b3 b2 b1 b0 0w/r ra4 ra3 ra2 ra1 ra0 0
cs5461 32 ds546pp2 6.2 serial port interface the cs5461?s serial interface consists of four con- trol lines, which have th e following pin-names: cs , sdi, sdo, and sclk. 1) cs is the control line which enables access to the serial port. if the cs pin is tied to logic 0, the port can function as a three wire interface. 2) sdi is the data signal used to transfer data to the converter. 3) sdo is the data signal used to transfer output data from the convert er. the sdo output will be held at high impedance any time cs is at logic 1. 4) sclk is the serial bit- clock which controls the shifting of data to or from the adc?s serial port. the cs pin must be held at logic 0 before sclk transitions can be recognized by the port logic. to accommodate opto-isolators sclk is designed with a schmitt- trigger input to allow an opto-isolator with slow er rise and fall times to directly drive the pin. 6.3 serial read and write the state machine decodes the command word as it is received. data is written to and read from the cs5461 by using the regist er read/write opera- tion. a transfer of data is always initiated by send- ing the appropriate 8-bit command (msb first) to the serial port (sdi pin). figure 1 illustrates the se- rial sequence necessary to wr ite to, or read from the serial port?s buffers. during a write operation, the serial port will contin- ue to clock in the data bi ts (msb first) on the sdi pin for the 24 sclk cycles. when a read command is initiated, the serial port will start transferring regi ster content bits serial (msb first) on the sdo pin for 8, 16, or 24 sclk cycles. command words instructing a register read may be terminated at 8-bit boundaries. also data register reads allow ?command chaining?. this means the micro-contro ller can send a new com- mand while reading register data. the new com- mand will be acted upon immediately and could possibly terminate the first register read. for exam- ple, if only the 16 most signi ficant bits of data from the first read are require d, a second read command on sdi can be initiated after the first 8 data bits are read from sdo. during a read cycle, the sync0 command (nop) should be strobed on the sdi port while clocking the data from the sdo port. 6.4 system initialization a software or hardware rese t can be initiated at any time. the software reset is initiated by sending the command 0x80. a hardware reset is initiated when the reset pin is forced low with a minimum pulse width of 50 ns. the reset signal is asynchronous, requiring no mclks for the part to detect and store a reset event. the reset pin is a schmit t trigger input, which allows it to accept slow rise times and/or noisy control signals. once the reset pin is inac- tive, the internal reset circuitry remains active for 5 mclk cycles to insure resetting the synchronous circuitry in the device. the modulators are held in reset for 12 mclk cycles after reset becomes in active. after a hardware or software reset, the in- ternal registers (some of which drive output pins) will be reset to their default values on the first mclk received after detecti ng a reset event. the in- ternal register values are also set to their default val- ues after initial power-on of the device. the cs5461 will then assume its active state.
cs5461 ds546pp2 33 6.5 serial port initialization it is possible for the seri al interface to become un- synchronized, with respec t to the sclk input. if this occurs, any attempt to clock valid cs5461 commands into the serial interface may result in unexpected operation. th e cs5461?s serial port must then be re-initialized. to initialize the serial port, any of the follow ing actions can be per- formed: 1) drive the cs pin low [or if cs pin is already low, drive the pin high, then back to low]. 2) hardware reset (drive reset pin low, for at least 10 s). 3) issue the serial port initialization sequence , which is performed by clocking 3 (or more) sync1 command bytes (0xff) followed by one sync0 command byte (0xfe). 6.6 cs5461 power states active state denotes the operation of cs5461 when the device is fully powered on (not in sleep state or stand-by state). to insure th at the cs5461 is oper- ating in the active state; perform one of the three actions below: 1) power on the cs5461. (or if the device is al- ready powered on, recycle the power.) 2) software reset 3) hardware reset if the device is in sleep state or in stand-by state, is- suing the power-up/halt command will also insure that the device is in active state. in order to send the power-up/halt command to the device, the serial port must be initialized. therefore, after applying power to the cs5461, a ha rdware reset should al- ways be performed.
cs5461 34 ds546pp2 7. register description 1. ?default**? => bit status after power-on or reset 2. any bit not labeled is reserved. a zero should al ways be used when writing to one of these bits. 7.1 configuration register address: 0 default** = 0x000001 pc[6:0] phase compensation. a 2?s complement numb er which sets the delay in the voltage channel. when mclk=4.096 mhz and k=1, the phase adjustment range is about -2.8 to +2.8 degrees and each step is about 0.04 de grees (assuming a power line frequency of 60 hz). if (mclk / k) is not 4.096 mhz, the values for the range a nd step size should be scaled by the factor 4.096mhz / (mclk / k). default setting is 0000000 = 0.0215 degrees phase delay at 60 hz (when mclk = 4.096 mhz). igain sets the gain of the current pga 0 = gain is 10 (default) 1 = gain is 50 ewa allows the eout and edir pins to be configured as open-collector output pins. 0 = normal outputs (default) 1 = only the pull-down device of the eout and edir pins are active [imode iinv] soft interrupt configurat ion bits. select the desired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (int is normally high) 11 = rising edge (int is normally low) epp allows the eout and edir pins to be controlled by the dl0 and dl1 bits. eout and edir can also be accessed using the status register. 0 = normal operation of the eout and edir pins. (default) 1 = eop and edp bits control the eout and edir pins. eop when epp = 1, eout becomes a user defined pin, and eop sets the value of the eout pin. default = '0' edp when epp = 1, edir becomes a user defined pin, edp sets the value of the edir pin. default = '0' vhpf control the use of the high pass filter on the voltage channel. 0 = high-pass filter disabled (default) 1 = high-pass filter enabled ihpf control the use of the high pass filter on the current channel. 23 22 21 20 19 18 17 16 pc6 pc5 pc4 pc3 pc2 pc1 pc0 igain 15 14 13 12 11 10 9 8 ewa imode iinv epp eop edp 76543210 vhpf ihpf icpu k3 k2 k1 k0
cs5461 ds546pp2 35 0 = high-pass filter disabled (default) 1 = high-pass filter enabled icpu inverts the cpuclk clock. in order to reduce the level of noise present when analog signals are sampled, the logic driven by cpuclk should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when cpuclk is driving rising edge logic k[3:0] clock divider. a 4-bit binary number used to divi de the value of mclk to generate the internal clock dclk. the internal clock frequency is dclk = mclk/k. the value of k can range be- tween 1 and 16. note that a value of ?0000? will set k to 16 (not zero). 7.2 dc current offset register and dc voltage offset register address: 1 (dc current offset register ); 3 (dc voltage offset register) default** = 0.000 the dc offset registers are initialized to zero on reset, a llowing for uncalibra ted normal operation. if dc offset calibration is performed, this register is updated after one computation cycle with the current or voltage offset if the proper dc input signals ar e applied. drdy will be asserted at the end of the calibration. this register may be read and stored for future system offset compensation. the value is in the range full scale. the numeric format of this register is two?s complement notation. 7.3 ac/dc current gain register and ac/dc voltage gain register address: 2 (current gain register); 4 (voltage gain register) default** = 1.000 the gain registers are initialized to 1.0 on reset, allowin g for uncalibrated normal operation. the gain registers hold the result of either the ac or dc gain calibrations, whichever was most recently performed. if dc calibration is performed, the register is updated after one computation cycle with the system gain when the proper dc input is applied. if ac calibration is perf ormed, then after ~(6n + 30) a/d conversion cycles (where n is the value of the cycle-count register) the register(s) is updated with the system gain when the prop er ac input is applied. drdy will be asserted at the end of t he calibration. the register may be read and stored for future system gain compensation. the value is in the range 0.0 gain < 3.9999. 7.4 cycle count register address: 5 default** = 4000 the cycle count register value (denoted as ?n?) determines the length of one energy and rms computation cycle . during continuous conversions, the co mputation cycle frequency is (mclk/k)/(1024 ? n). msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0
cs5461 36 ds546pp2 7.5 pulseratee register address: 6 default** = 32000.00 hz the pulseratee register determines the averag e frequency of the pulses issued on the eout output pin. the register?s smallest valid value is 2 -4 but can be in 2 -5 increments. a pulserate high er than mclk/k/8 will result in a pulse rate setting of mclk/k/8. 7.6 i, v, p, & p avg : instantaneous current, voltage, po wer, and average power (signed) output register address: 7 - 10 these signed registers cont ain the last measured value of i, v, p, and p avg . the results will be within in the range of -1.0 i,v,p,p avg < 1.0. the value is represented in two's co mplement notation, with the binary point place to the right of the msb (msb has a negative weightin g). these values are 22 bits in length. the two least significant bits have no meaning, and will always have a value of ?0?. 7.7 i rms , v rms unsigned output register address: 11,12 these unsigned registers contain the last values of i rms and v rms . the results are in the range of 0.0 i rms ,v rms < 1.0. the value is represented in (unsigned) bina ry notation, with the binary point place to the left of the msb. these results are updated after each computation cycle. 7.8 timebase calibration register address: 13 default** = 1.000 this register can be set with a clock frequency error co mpensation value, to corre ct for a gain/timing error caused by the crystal/oscillator toler ance. the value is in the range 0.0 tbc < 2.0. msb lsb 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 ..... 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5461 ds546pp2 37 7.9 power offset register address: 14 default** = 0.000 this offset value is added to each power value that is computed for each voltage/current sample pair before being accumulated in the energy register. this register c an be used to offset contribu tions to the energy result that are caused by undesirable sources of energy that are inhere nt in the system. this va lue is in two?s comple- ment notation. 7.10 status register and mask register address: 15 ( status register ) ; 26 (mask register) default** = 0x000000 (status register) 0x000000 (mask register) the status register indicate s the condition of the chip. in normal operat ion writing a '1' to a bit will cause the bit to go to the '0' state. writin g a '0' to a bit will maintain t he status bit in its current stat e. with this feature the user can simply write to the status register to clear the bi ts that have been seen, without concern of clearing any newly set bits. even if a status bit is masked to prevent an interrupt, the status bi t will still be set in the status register. the mask register is used to cont rol the activation of the int pin. placing a logic '1' in the mask register will allow the corresponding bit in the status register to activate the int pin when the status bit is asserted. drdy data ready. when running in single or continuous conversion acquisition mode, this bit will in- dicate the end of computation cycles. when runni ng calibrations, this bit indicates the end of a calibration sequence. eout indicates that the energy limit has been reached for the eout energy accumulation register, and so this register will be cleared, and one pulse will be generated on the eout pin (if en- abled). if eout is asserted, this bit will be cleared automatically just after the beginning of any subsequent a/d conversion cycle in which no eout pulses need to be issued. the bit can also be cleared by writing to the stat us register. this status bit is set with a maximum frequency of 4 khz (when mclk/k is 4.096 mhz). when mclk/k is not equal to 4.096 mhz, the user should scale the pulse-rate would be expected with mc lk/k = 4.096 mhz by a factor of 4.096 mhz / (mclk/k), to get the actual pulse-rate. edir set whenever the eout bit is asserted as long as the ener gy result is negative. reset/clear behavior of the edir status bit is similar to the eout status bit. ior current out of range. set when the magnitude of the calibrated current value is too large or too small to fit in the inst antaneous current register. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 23 22 21 20 19 18 17 16 drdy eout edir crdy ior vor 15 14 13 12 11 10 9 8 iror vror eoor 76543210 vod iod lsd vsag ic
cs5461 38 ds546pp2 crdy conversion ready. indicates a ne w conversion is ready. this will occur at the output word rate. vor voltage out of range. vsag indicates that the voltag e threshold/duration condit ions, specified in the vsag level and vsag duration registers, have been met. vror rms voltage out of range. set when the calibrated rms voltage va lue is too large to fit in the rms voltage register. iror rms current out of range. set when the calibrate d rms current value is too large to fit in the rms current register. eoor eout energy summation register out of range. as sertion of this bit ca n be caused by having a pulse output frequency that is too small for the power being measured. this problem can be corrected by specifying a higher frequency in the pulseratee register. vod modulator oscillation detect on the voltage channel. set when t he modulator oscillates due to an input above full scale. note that the level at which the modul ator oscillates is significantly higher than the voltage channel?s differential input voltage range. iod modulator oscillation detect on the current channel. set when the modulator oscillates due to an input above full scale. note that the level at which the modu lator oscillates is significantly higher than the current channel?s differential input voltage range. note: the iod and vod bits may be ?falsely? triggered by very brief voltage spikes from the power line. this event should not be confused with a dc overload situation at the inputs, when the iod and vod bits will re-assert themselves even after being cleared, multiple times. lsd low supply detect. set when the voltage at th e pfmon pin falls below the low-voltage thresh- old (pmlo), with respect to va- pin. for a given part, pmlo can be as low as 2.3 v. lsd bit cannot be permanently reset until the voltage at pfmon pin rises back above the high-voltage threshold (pmhi), which is typically 100 mv abov e the device?s low-volt age threshold. pmhi will never be greater than 2.7 v. ic invalid command. normally logic 1. set to logic 0 if the host inte rface is strobed with an 8-bit word that is not recognized as one of the valid commands (see section 6.1, commands ). 7.11 ac current offset register and ac voltage offset register address: 16 (ac current offset register ); 17 (ac voltage offset register) default** = 0x000000 the ac offset registers are initialized to zero on reset, allowing for uncalibrated normal operation. when ac offset calibration is performed, the of fset register(s) is updated with the sq uare of the system ac offset value. this sequence lasts ~(6n + 30) a/d conversion cycles (where n is the va lue of the cycle-count register). drdy will be asserted at the end of the calibration. the regi ster value may be read and stored for future system offset compensation. msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24
cs5461 ds546pp2 39 7.12 pulseratef register address: 18 default** = 32000.00 hz the pulseratef register sets the average pulse frequency of the fout output pin. the register?s smallest valid value is 2 -4 but can be in 2 -5 increments. a pulserate higher than mclk/k/8 will resu lt in a pulse rate setting of mclk/k/8. 7.13 temperature sensor output register address: 19 this signed register contains the ou tput of the on-chip temperature sensor. the results are in the range of -128.0 t < 128.0. the value is represented in unsigned binary notation, with the binary point place to the left of the msb. this result is upda ted after each computation cycle. 7.14 pulsewidth address: 21 default** = 512 sample periods this signed register determines the pulsewidth of eout and edir pulses in mechanical counter mode. the width is set in number of sample periods. the default is 512. this corresponds to a pulsewidth of 512 samples / [(mclk/k)/1024] = 128 msec with mclk = 4.0 96 mhz and k = 1. although this is a signed reg- ister a negative value will have no meaning; pulsewidth se ttings must be positive. 7.15 vsag level : voltage sag-detect threshold level address: 23 default** = 0x000000 this signed register se ts the threshold le vel for the voltag e sag detect feature. to activate the vsag bit the status register, the value of the v rms register must remain be low this threshold level for a set number of sam- ples (defined in the vsagduration regist er). voltage threshold le vels must be positive values; a negative value can be used to disable the feature. for more information about the voltage sag detect functionality, refer to sec- tion 4.10 of the data sheet. msb lsb 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 ..... 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5461 40 ds546pp2 7.16 vsag duration : voltage sag-detect duration level address: 24 default** = 0x000000 this register sets the number of conversions over to accumulate rms voltage for comparison against the vsa- g level . setting this register to ze ro will disable the vsag feature. 7.17 control register register address: 28 default** = 0x000000 fac 1 = enable anti-creep for fout pulse output function. eac 1 = enable anti-creep for eout pulse output function. stop 1 = used to terminate the new eeboot sequence. mech 1 = widens eout and edir pulses for mechanical counters. intod 1 = converts int output to open drain configuration. nocpu 1 = saves power by disablin g the cpuclk external drive pin. noosc 1 = saves power by disablin g the crystal oscillator circuit. step 1 = enables stepper-motor signals on the eout /edir pins. msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 fac eac stop 76543210 mech intod nocpu noosc step
cs5461 ds546pp2 41 8. basic application circuits figure 14 shows the cs5461 connected to a service to measure power in a si ngle-phase 2-wire system while operating in a singl e supply configuration. note that in this diagram the shunt resistor used to monitor the line current is connected on the ?line? (hot) side of the power ma ins. in most residential power metering applicati ons, the power meter?s current-sense shunt resistor is intentionally placed on the hot side of the power mains in order to detect a subscriber?s attempt to st eal power. in this type of shunt-resistor configur ation, the common-mode level of the cs5461 must be referenced to the hot side of the power line; which means the com- mon-mode potential of the cs5461 will typically oscillate to very high volta ge levels with respect to earth ground potential. if digital communication networks require that the cmos-level digital inter- face be referenced to an earth ground, the serial in- terface pins on the cs5461 must be isolated from the external digital interface. figure 15 shows the same single-phase two-wire system with complete is olation from the power lines. this isolation is achieved using three trans- formers: a general purpos e transformer to supply the on-board dc power; a high-precision, low im- pedance voltage transfor mer, with very little roll-off/phase-delay, to m easure voltage; and a cur- rent transformer to sense the line current. because the cs5461 is not directly connected to the power mains, no isolation is necessary on the cs5461?s digital interface. figure 16 shows a single-pha se 3-wire system. in many 3-wire reside ntial power systems within the united states, only the two line terminals are avail- able (neutral is not available). figure 17 shows the cs5461 configured to mete r a three-wire system with no neutral available. va+ vd+ cs5461 0.1 f 100 f 500 ? 470 nf 500 n r 1 r 2 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin optional clock source serial data interface reset 17 2 1 24 19 cs 7 sdi 23 sdo 6 sclk 5 int 20 edir eout 0.1 f vrefin 12 vrefout 11 va- dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f c 10 k ? 5k ? l r shunt v+ r v- r i- r i+ c i+ isolation 120 vac mech. counter stepper motor or 22 21 figure 14. typical connectio n diagram (one-phase 2-wire, direct connect to power
cs5461 42 ds546pp2 va+ vd+ cs5461 0.1 f 200 f 200 n 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sdi sdo sclk int edir 22 eout 21 0.1 f vrefin 12 vrefout 11 va- dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f 10 k ? 5k ? l m:1 r n:1 low phase-shift potential transformer current transformer r v+ r v- c vdiff r i- r i+ c burden idiff voltag e transforme r 120 vac 12 vac 12 vac ? 200 ? serial data interface 19 7 23 6 5 20 mech. counter stepper motor or 1k ? 1k ? 1k ? 1k ? figure 15. typical connection diagram (one -phase 2-wire, isolated from power line) va+ vd+ cs5461 0.1 f 100 f 500 ? 470 nf 500 ? n r 3 r 4 r burden 10 ? 14 vin+ 9 vin- iin- 10 16 15 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sd sdo sclk int edir eout 0.1 f vrefin 12 vrefout 11 dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f l 1 l 2 10 k ? 5k ? va- r 1 r 2 to service r i+ r i- 22 21 mech. counter stepper motor or 1k ? 1k ? 120 vac 120 vac 240 vac serial data interface 19 7 23 6 5 20 i earth ground c idiff c idiff figure 16. typical connectio n diagram (one-phase 3-wire)
cs5461 ds546pp2 43 va+ vd+ 0.1 f 100 f 1 k ? 235 nf 500 ? r 1 r 2 10 ? 14 vin+ 9 vin- iin- 10 16 15 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sdi sdo sclk int edir eout 0.1 f vrefin 12 vrefout 11 dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f l 1 l 2 10 k ? 5k ? va- c v+ to service r i+ r i- r v- serial data interface 19 7 23 6 5 20 isolation 22 21 mech. counter stepper motor or r burden 1k ? 1k ? 240 vac cs5461 figure 17. typical connection diagram (o ne-phase 3-wire - no neutral available)
cs5461 44 ds546pp2 9. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters. 24l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5461 ds546pp2 45 10. revisions revision date changes a1 march 2003 initial release pp1 13 october 2003 initial release for preliminary product information pp2 5 december 2003 1) added auto-boot feature de scription (page page 1, 6, 12, 27, 28, 37, 13) 2) added mode pin functionality (page 6, 12, 27) contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the informat ion is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version o f relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patent s or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any p atents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. ci rrus owns the copyrights associated with the information con tained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or techn ologies described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license an d/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is s ubject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potentia l risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). ci rrus products are not designed, authorized or warranted for use in aircraft systems, military applicatio ns, products surgically im planted into the body, life support products or oth- er critical applications (including medica l devices, aircraft systems or components and personal or automotive safety or security devices). inclusion of cirrus pr oducts in such applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implie d warranties of merchantability and fitness for particular purpos e, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, direct ors, employees, distributors and other agents from any and all liability, includ- ing attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
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